1. Field of the Invention
This invention relates generally to switching converters, and more particularly to switching converters which employ an emulated peak current mode control scheme.
2. Description of the Related Art
One control scheme for a switching power converter is known as emulated peak current mode; an example is shown in FIG. 1. The converter receives a supply voltage VIN and produces an output voltage VOUT; VOUT is divided by a voltage divider 10 to produce a feedback voltage FB. An error amplifier 12 receives FB and a reference voltage Vref at respective inputs and produces an output labeled ‘comp’. In operation, high side and low side switching elements 14, 16 are driven with a signal pwm_d# produced by an SR latch 17, with pwm_d# going low and turning on switching element 14 each time the latch gets set with a clock signal 18. Signal ‘comp’ and a signal ‘ramp’ are compared with a PWM comparator 19, the output of which resets SR latch 17.
A current sensing circuit 20 senses the inductor current: if the converter is configured as a ‘buck’ converter, the current sensing circuit senses the current in low side switching element 16; if configured as a boost converter, the current in high side switching element 14 is sensed. The sensed current is used to provide the ‘ramp’ signal when the inductor current is negative—i.e., during the converter's ‘off’ time when the low side switching element is on. To emulate the positive inductor current, a current proportional to VIN−VOUT is connected to a capacitance 22; a slope compensation current Islp—cmp may also be applied to capacitance 22 under some conditions. When the SR latch gets ‘set’, the signal on capacitance 22 is added to the sensed current (via a switch 24) and converted into a voltage (via a resistance 26) to form the ‘ramp’ signal. A diagram depicting typical ‘comp’ and ‘ramp’ signals is shown in FIG. 1.
For an emulated peak current mode control scheme, the current sense amp is connected to the synchronous switch (16 for the buck converter shown) instead of the main switch (14). Current sensing is done during the ‘off’ time, with an emulated slope that causes the ‘ramp’ signal to increase linearly with a rate that varies with VIN−VOUT generated during the ‘on’ time. This emulated slope is used at the ‘off’ to ‘on’ transition such that, even when the duty cycle is small, the slope is not affected by switching noise that might adversely affect other control schemes such as true peak current mode. This also avoids the need to provide a ‘blanking time’ at the ‘off’ to ‘on’ transition, as is common with a true peak current mode control scheme.
However, with an emulated peak current mode control scheme, the ratio of the emulated current slope and the slope of the actual sensed current can vary greatly, as the values of components external to the circuit are usually unknown, and the emulated slope may be changed by process or temperature variations. This is illustrated in FIG. 2a, in which the emulated positive slope 28 portion of ‘ramp’ signal 29 can vary over a range of values (30) as shown. If the emulated current slope is less than the actual sensed current slope, this may cause sub-harmonic oscillation. To prevent sub-harmonic oscillation, the emulated current slope is sometimes made much steeper than the actual sensed current slope; this is illustrated in FIG. 2b. However, in this case, system operation is closer to voltage mode than current mode, and the response tends to be slow.